Semiconductor memory devices are provided with a redundancy function to replace a defective memory cell with a redundancy memory cell that is a backup memory cell. Memory cell operations are tested at the time of shipment of a semiconductor memory device. Upon finding a defective memory cell, the address of this defective memory cells is recorded in a fuse circuit or the like. An address to be accessed that is applied from an external device may match the address of the defective memory cell that is recorded in the fuse circuit. Upon such an event, an access location is switched to a redundant memory cell, thereby causing the redundant memory cell, rather than the defective memory cell, to be accessed. With this arrangement, the address of the defective memory cell is made usable. In general, a redundancy replacement operation is performed on a word-line-by-word-line basis or a column-line-by-column-line basis.
The use of a redundant memory cell is avoided if this redundant memory cell is defective. To this end, a test to check the operations of a semiconductor memory device preferably includes not only a test to check primary memory cell operations but also a test to check redundant memory cell operations. With the configuration that performs a redundancy replacement on a word-line-by-word-line basis, for example, all the primary word lines and all the redundant word lines are tested for operations. In general, every access is performed with respect to a primary word line if no recording has been made to the fuse circuit. In order to test redundant word line operations, thus, a test mode that specifies a redundant line test is activated. Access to a desired redundant word line is then performed by specifying an address assigned to this redundant word line. Performing of a redundancy operation in such a forcible manner is referred to as “forced redundancy”
DRAM (Dynamic Random Access Memory) performs a refresh operation with respect to each memory cell at constant intervals in order to retain memory cell data. A refresh command may be applied from an external source to perform a refresh operation. Alternatively, a refresh timing and address are generated inside the semiconductor memory device by an internal refresh mechanism to perform a refresh operation. A refresh operation initiated by the internal refresh mechanism is also used during the test that checks memory cell operations such as a disturb test.
When the forced redundancy described above is activated, however, a primary word line having an address assigned to a redundant word line may not be accessed. A refresh operation initiated by the internal refresh mechanism is thus not performed with respect to this primary word line. When the forced redundancy is not activated, a redundant word line may not be accessed. A refresh operation initiated by the internal refresh mechanism is thus not performed with respect to this redundant word line. In this manner, the activation of forced redundancy leads to a situation in which the performance of a primary word line is not properly tested, and the deactivation of forced redundancy leads to a situation in which the performance of a redundant word line is not properly tested. Consequently, a test to check the operation of redundant word lines and a test to check the operation of primary word lines may need to be performed one by one.
Patent Document 1 discloses a synchronous DRAM that refreshes main cells and backup cells successively at the time of auto refresh operation in a test mode. Patent Document 2 discloses a DRAM that is capable of reducing a test time by refreshing normal cells and redundant cells at the same time. Patent Document 3 discloses a semiconductor memory provided with an access mechanism to access all the real cells and redundant cells in the same address space at the time of test.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2000-357398
[Patent Document 2] Japanese Laid-open Patent Publication No. 2003-297092
[Patent Document 3] Japanese Laid-open Patent Publication No. 09-293394